TraceRTL: Agile Performance Evaluation for Microarchitecture Exploration

Zifei Zhang; Yinan Xu; Kaichen Gong; Sa Wang; Dan Tang; Yungang Bao

Authors

Zifei Zhang State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, 100190, Beijing, China , University of Chinese Academy of Sciences, 100190, Beijing, China Author
Yinan Xu State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, 100190, Beijing, China Author
Kaichen Gong School of Information Science and Technology, ShanghaiTech University, 200000, Shanghai, China Author
Sa Wang State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, 100190, Beijing, China , University of Chinese Academy of Sciences, 100190, Beijing, China Author
Dan Tang State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, 100190, Beijing, China , Beijing Institute of Open Source Chip, 100080, Beijing, China Author
Yungang Bao State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, 100190, Beijing, China , University of Chinese Academy of Sciences, 100190, Beijing, China Author

Keywords:

Trace-driven simulation, Performance evaluation, Cross ISA benchmarking

Abstract

While agile chip development methodologies have accelerated RTL design and simulation, performance evaluation remains constrained by challenges:
(1) limited benchmarks availability due to incomplete peripheral/software simulation environments or unavailable source code;
(2) inefficient feature prototyping caused by the tight coupling between functional correctness and performance evaluation, particularly for large‑scale, error‑prone microarchitectures.
To address these challenges, we propose TraceRTL, an agile, trace-driven performance evaluation methodology that decouples the functional and performance components of CPU RTL designs.
It introduces three contributions to benchmarking community: (1) a trace‑driven exploration framework that bypasses full functional correctness while preserving performance behavior and supports to replay workload traces on RTL designs; (2) a quantitative analysis and mitigation methodology to identify and reduce trace-driven performance discrepancies; (3) a trace transformation technique, TraceBridge, that replays benchmark traces across different formats and instruction sets.
Using TraceRTL, we develop the first trace-driven RTL CPU derived from XiangShan, a high-performance out-of-order RISC-V processor.
TraceRTL achieves performance accuracies of 99.87% and 99.86% on SPECint2017 and SPECfp2017, respectively.
With TraceBridge, we evaluate x86-based Google workload traces on a RISC-V RTL CPU and reveal distinct memory-bound behavior.

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