TraceRTL: Agile Performance Evaluation for Microarchitecture Exploration
DOI:
https://doi.org/10.66834/5s84yp08Keywords:
Trace-driven simulation, Performance evaluation, Cross ISA benchmarkingAbstract
While agile chip development methodologies have accelerated RTL design and simulation, performance evaluation remains constrained by challenges:
(1) limited benchmarks availability due to incomplete peripheral/software simulation environments or unavailable source code;
(2) inefficient feature prototyping caused by the tight coupling between functional correctness and performance evaluation, particularly for large‑scale, error‑prone microarchitectures.
To address these challenges, we propose TraceRTL, an agile, trace-driven performance evaluation methodology that decouples the functional and performance components of CPU RTL designs.
It introduces three contributions to benchmarking community: (1) a trace‑driven exploration framework that bypasses full functional correctness while preserving performance behavior and supports to replay workload traces on RTL designs; (2) a quantitative analysis and mitigation methodology to identify and reduce trace-driven performance discrepancies; (3) a trace transformation technique, TraceBridge, that replays benchmark traces across different formats and instruction sets.
Using TraceRTL, we develop the first trace-driven RTL CPU derived from XiangShan, a high-performance out-of-order RISC-V processor.
TraceRTL achieves performance accuracies of 99.87% and 99.86% on SPECint2017 and SPECfp2017, respectively.
With TraceBridge, we evaluate x86-based Google workload traces on a RISC-V RTL CPU and reveal distinct memory-bound behavior.
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